[PATCH] D58899: [CodeGen] Prepare for introduction of v3 and v5 MVTs

[Tim Renouf via Phabricator via llvm-commits]

tpr created this revision.
Herald added subscribers: llvm-commits, jdoerfert, kristof.beyls, javed.absar, nhaehnle, jvesely, arsenm.
Herald added a project: LLVM.

AMDGPU would like to have MVTs for v3i32, v3f32, v5i32, v5f32. This
commit does not add them, but makes preparatory changes:

- Exclude non-legal non-power-of-2 vector types from ComputeRegisterProp mechanism in TargetLoweringBase::getTypeConversion.

- Cope with SETCC and VSELECT for odd-width i1 vector when the other vectors are legal type.

- Fixed an assumption of power-of-2 vector type in ARM.

- Fixed assumptions of power-of-2 vector type in AMDGPU kernel arg handling.

- Fixed AMDGPU cost analysis to behave the same.

Some of this patch is from Matt Arsenault, also of AMD.

Change-Id: Ib5f23377dbef511be3a936211a0b9f94e46331f8


Repository:
  rL LLVM

https://reviews.llvm.org/D58899

Files:
  include/llvm/CodeGen/SelectionDAG.h
  lib/CodeGen/SelectionDAG/LegalizeTypes.h
  lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
  lib/CodeGen/SelectionDAG/SelectionDAG.cpp
  lib/CodeGen/TargetLoweringBase.cpp
  lib/Target/AMDGPU/AMDGPUISelLowering.cpp
  lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
  lib/Target/ARM/ARMISelLowering.cpp

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D58899.189142.patch
Type: text/x-patch
Size: 8123 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20190304/d960dc62/attachment.bin>