[llvm] r354161 - [X86] Move all the SSE legality checks out of FP_TO_INTHelper and up to LowerFP_TO_INT. NFCI

[Craig Topper via llvm-commits]

Author: ctopper
Date: Fri Feb 15 11:21:39 2019
New Revision: 354161

URL: http://llvm.org/viewvc/llvm-project?rev=354161&view=rev
Log:
[X86] Move all the SSE legality checks out of FP_TO_INTHelper and up to LowerFP_TO_INT. NFCI

These checks aren't needed on the call to FP_TO_INTHelper from the type legalizer for splitting i64. We always want to use X87 FIST/FISTT to memory there.

Moving up the SSE checks will allow this routine to focus on what it cares about and makes its return semantics cleaner.

Modified:
    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=354161&r1=354160&r2=354161&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Fri Feb 15 11:21:39 2019
@@ -18066,13 +18066,10 @@ SDValue X86TargetLowering::LowerUINT_TO_
 
 // If the given FP_TO_SINT (IsSigned) or FP_TO_UINT (!IsSigned) operation
 // is legal, or has an fp128 or f16 source (which needs to be promoted to f32),
-// just return an <SDValue(), SDValue()> pair.
+// just return an SDValue().
 // Otherwise it is assumed to be a conversion from one of f32, f64 or f80
-// to i16, i32 or i64, and we lower it to a legal sequence.
-// If lowered to the final integer result we return a <result, SDValue()> pair.
-// Otherwise we lower it to a sequence ending with a FIST, return a
-// <FIST, StackSlot> pair, and the caller is responsible for loading
-// the final integer result from StackSlot.
+// to i16, i32 or i64, and we lower it to a legal sequence and return the
+// result.
 SDValue
 X86TargetLowering::FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
                                    bool IsSigned) const {
@@ -18091,14 +18088,9 @@ X86TargetLowering::FP_TO_INTHelper(SDVal
   // If using FIST to compute an unsigned i64, we'll need some fixup
   // to handle values above the maximum signed i64.  A FIST is always
   // used for the 32-bit subtarget, but also for f80 on a 64-bit target.
-  bool UnsignedFixup = !IsSigned &&
-                       DstTy == MVT::i64 &&
-                       (!Subtarget.is64Bit() ||
-                        !isScalarFPTypeInSSEReg(TheVT));
+  bool UnsignedFixup = !IsSigned && DstTy == MVT::i64;
 
   if (!IsSigned && DstTy != MVT::i64) {
-    assert(!Subtarget.hasAVX512() &&
-           "AVX512 should have already been handled!");
     // Replace the fp-to-uint32 operation with an fp-to-sint64 FIST.
     // The low 32 bits of the fist result will have the correct uint32 result.
     assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
@@ -18109,12 +18101,6 @@ X86TargetLowering::FP_TO_INTHelper(SDVal
          DstTy.getSimpleVT() >= MVT::i16 &&
          "Unknown FP_TO_INT to lower!");
 
-  // These are really Legal.
-  if (DstTy == MVT::i32 && isScalarFPTypeInSSEReg(TheVT))
-    return SDValue();
-  if (Subtarget.is64Bit() && DstTy == MVT::i64 && isScalarFPTypeInSSEReg(TheVT))
-    return SDValue();
-
   // We lower FP->int64 into FISTP64 followed by a load from a temporary
   // stack slot.
   MachineFunction &MF = DAG.getMachineFunction();
@@ -18737,9 +18723,11 @@ SDValue X86TargetLowering::LowerFP_TO_IN
 
   assert(!VT.isVector());
 
+  bool UseSSEReg = isScalarFPTypeInSSEReg(SrcVT);
+
   if (!IsSigned && Subtarget.hasAVX512()) {
     // Conversions from f32/f64 should be legal.
-    if (SrcVT != MVT::f80)
+    if (UseSSEReg)
       return Op;
 
     // Use default expansion.
@@ -18748,17 +18736,21 @@ SDValue X86TargetLowering::LowerFP_TO_IN
   }
 
   // Promote i16 to i32 if we can use a SSE operation.
-  if (VT == MVT::i16 && isScalarFPTypeInSSEReg(SrcVT)) {
+  if (VT == MVT::i16 && UseSSEReg) {
     assert(IsSigned && "Expected i16 FP_TO_UINT to have been promoted!");
     SDValue Res = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, Src);
     return DAG.getNode(ISD::TRUNCATE, dl, VT, Res);
   }
 
+  // If this is a SINT_TO_FP using SSEReg we're done.
+  if (UseSSEReg && IsSigned)
+    return Op;
+
+  // Fall back to X87.
   if (SDValue V = FP_TO_INTHelper(Op, DAG, IsSigned))
     return V;
 
-  // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
-  return Op;
+  llvm_unreachable("Expected FP_TO_INTHelper to handle all remaining cases.");
 }
 
 static SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) {