[PATCH] D58197: [x86] vectorize more cast ops in lowering to avoid register file transfers
Sanjay Patel via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Feb 13 13:43:27 PST 2019
spatel marked an inline comment as done.
spatel added inline comments.
Comment at: llvm/test/CodeGen/X86/known-signbits-vector.ll:79
; X64-NEXT: shrq $32, %rax
; X64-NEXT: vcvtsi2ssl %eax, %xmm1, %xmm0
; X64-NEXT: retq
> Any idea why this still fails?
This is almost the same example as in:
On x86-64 only (because the 64-bit shift isn't legal on i686), we scalarize the shift. So that means we have the shift sitting between the extract and cast, so no match.
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