[PATCH] D58197: [x86] vectorize more cast ops in lowering to avoid register file transfers
Simon Pilgrim via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Thu Feb 14 04:17:59 PST 2019
RKSimon added inline comments.
Comment at: llvm/test/CodeGen/X86/known-signbits-vector.ll:79
; X64-NEXT: shrq $32, %rax
; X64-NEXT: vcvtsi2ssl %eax, %xmm1, %xmm0
; X64-NEXT: retq
> RKSimon wrote:
> > Any idea why this still fails?
> This is almost the same example as in:
> On x86-64 only (because the 64-bit shift isn't legal on i686), we scalarize the shift. So that means we have the shift sitting between the extract and cast, so no match.
Hmm - is it worth us investigating a trunc(lshr(extract(v2i64 x, i), 32)) -> trunc(extract(v2i64 x, i+1)) combine? (and variants)
CHANGES SINCE LAST ACTION
More information about the llvm-commits