[PATCH] D53235: [RISCV] Add RV64F codegen support

[James Clarke via Phabricator via llvm-commits]

jrtc27 added inline comments.


================
Comment at: test/CodeGen/RISCV/float-arith.ll:148
+; RV64IF-NEXT:    fmv.x.w a0, ft0
+; RV64IF-NEXT:    ret
   %1 = fsub float -0.0, %a
----------------
lewis-revill wrote:
> Can RV64 employ the same technique as RV32 here, and for other similar DAG combines? I'm guessing cost-wise it would be desirable to do so.
It should work, since `fmv.x.w` sign-extends:

> For RV64, the higher 32 bits of the destination register are filled with copies of the floating-point number’s sign bit.

and the `lui` will also sign-extend, so `xor` will flip all the higher bits too.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D53235/new/

https://reviews.llvm.org/D53235