[PATCH] D53235: [RISCV] Add RV64F codegen support

[Alex Bradbury via Phabricator via llvm-commits]

asb updated this revision to Diff 183618.
asb marked 4 inline comments as done.
asb edited the summary of this revision.
asb added a comment.

Changes since last time:

- Use custom legalisation rather than DAG combines to produce the f32 <-> i64 nodes
- Add target DAG combines that perform the equivalent of the (bitcast (fneg/fabs x)) conversion that the DAGCombiner does
- Rename target-specific SelectionDAG nodes to match the RISC-V fmv instruction naming.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D53235/new/

https://reviews.llvm.org/D53235

Files:
  lib/Target/RISCV/RISCVISelLowering.cpp
  lib/Target/RISCV/RISCVISelLowering.h
  lib/Target/RISCV/RISCVInstrInfoF.td
  test/CodeGen/RISCV/float-arith.ll
  test/CodeGen/RISCV/float-bitmanip-dagcombines.ll
  test/CodeGen/RISCV/float-br-fcmp.ll
  test/CodeGen/RISCV/float-convert.ll
  test/CodeGen/RISCV/float-fcmp.ll
  test/CodeGen/RISCV/float-imm.ll
  test/CodeGen/RISCV/float-mem.ll
  test/CodeGen/RISCV/float-select-fcmp.ll
  test/CodeGen/RISCV/rv32i-rv64i-float-double.ll
  test/CodeGen/RISCV/rv64f-float-convert.ll

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D53235.183618.patch
Type: text/x-patch
Size: 69487 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20190125/a0995478/attachment.bin>