[PATCH] D53235: [RISCV] Add RV64F codegen support

[Lewis Revill via Phabricator via llvm-commits]

lewis-revill added inline comments.


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Comment at: lib/Target/RISCV/RISCVISelLowering.cpp:636
+    // If the input to BitcastAndSextF32ToI64 is just TruncAndBitcastI64ToF32
+    // then the operation is redundnat. Instead, use TruncAndBitcastI64ToF32
+    // operand directly.
----------------
Typo 'redundant'


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Comment at: test/CodeGen/RISCV/float-arith.ll:148
+; RV64IF-NEXT:    fmv.x.w a0, ft0
+; RV64IF-NEXT:    ret
   %1 = fsub float -0.0, %a
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Can RV64 employ the same technique as RV32 here, and for other similar DAG combines? I'm guessing cost-wise it would be desirable to do so.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D53235/new/

https://reviews.llvm.org/D53235