[PATCH] D56082: [X86][SLP] Enable SLP vectorization for 128-bit horizontal X86 instructions (add, sub)

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added a comment.

Instead of being so explicit, why can't we just partially use a known legal vector width, maybe limited to subvectors that fit into the legal type (float2/int2/char4 etc.) - leaving the upper elements as undef/duplicates of the partial subvector? The cost model will likely be using the legal widths anyhow..

@craig.topper may have some thoughts on this patch's effects on D55251 <https://reviews.llvm.org/D55251> - vector widening legalization


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  https://reviews.llvm.org/D56082/new/

https://reviews.llvm.org/D56082