[PATCH] D56082: [X86][SLP] Enable SLP vectorization for 128-bit horizontal X86 instructions (add, sub)

[Anton Afanasyev via Phabricator via llvm-commits]

anton-afanasyev added a comment.

In D56082#1341234 <https://reviews.llvm.org/D56082#1341234>, @RKSimon wrote:

> Instead of being so explicit, why can't we just partially use a known legal vector width, maybe limited to subvectors that fit into the legal type (float2/int2/char4 etc.) - leaving the upper elements as undef/duplicates of the partial subvector? The cost model will likely be using the legal widths anyhow..
>
> @craig.topper may have some thoughts on this patch's effects on D55251 <https://reviews.llvm.org/D55251> - vector widening legalization


Hi Simon, yes, if I understand you correctly, that is exactly the conclusion I came to. I've investigated `getMinVectorRegisterBitWidth()` uses, the only its user is `SLPVectorizer` itself and it makes sense just to change `MinVectorRegisterBitWidth` to `64` for x86 target. I've looked for cases when cost model cannot process this but it woks well. Several new cases open with this change -- for instrs like PSUB[B|W|D] working with MMX 64-bit registers. Also cost model allows partial subvector operatioins.

So I propose just changing `MinVectorRegisterBitWidth` to `64` for x86 (like for aarch64). All the subtle tuning should be done by cost model.
I'm to edit revision accordingly.


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