[PATCH] D55448: [DAGCombiner] allow hoisting vector bitwise logic ahead of truncates

Thu Dec 13 16:00:33 PST 2018

spatel marked 2 inline comments as done.
spatel added a comment.

In D55448#1330392 <https://reviews.llvm.org/D55448#1330392>, @lebedev.ri wrote:

> > We already do this for scalars.
>
> Hm, are you sure?
>  I think i saw the opposite happen.
>  https://bugs.llvm.org/show_bug.cgi?id=36419#c4

Well, it's SDAG, so anything can happen. :)
My comment was specifically referring to the check that I'm hoping to change in this patch - it has a scalar-only restriction currently, and I think as the diffs here show, it's unnecessary.

================
Comment at: test/CodeGen/ARM/setcc-logic.ll:28
+; CHECK-NEXT:    lsr r0, r0, #5
+; CHECK-NEXT:    bx lr
   %cmp1 = icmp eq i32 %a, %b
----------------
RKSimon wrote:
> Is this a NFC regeneration change?
Yes, that's only adding the "-NEXT"; I can update it separately.

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https://reviews.llvm.org/D55448