[PATCH] D55448: [DAGCombiner] allow hoisting vector bitwise logic ahead of truncates

Roman Lebedev via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Thu Dec 13 14:05:45 PST 2018

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lebedev.ri added a comment.

> We already do this for scalars.

Hm, are you sure?
I think i saw the opposite happen.
https://bugs.llvm.org/show_bug.cgi?id=36419#c4


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https://reviews.llvm.org/D55448

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