[PATCH] D55448: [DAGCombiner] allow hoisting vector bitwise logic ahead of truncates

[Sanjay Patel via Phabricator via llvm-commits]

spatel updated this revision to Diff 178232.
spatel marked an inline comment as done.
spatel added a comment.

Patch updated:
No code changes, but rebased to remove cosmetic diffs in ARM test and updated codegen for x86 vector rotates.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D55448/new/

https://reviews.llvm.org/D55448

Files:
  lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  test/CodeGen/ARM/setcc-logic.ll
  test/CodeGen/Hexagon/autohvx/bitwise-pred-128b.ll
  test/CodeGen/Hexagon/autohvx/bitwise-pred-64b.ll
  test/CodeGen/X86/avx512-select.ll
  test/CodeGen/X86/bitcast-and-setcc-128.ll
  test/CodeGen/X86/bitcast-and-setcc-256.ll
  test/CodeGen/X86/bitcast-and-setcc-512.ll
  test/CodeGen/X86/psubus.ll
  test/CodeGen/X86/vector-rotate-128.ll
  test/CodeGen/X86/vector-rotate-256.ll
  test/CodeGen/X86/vector-rotate-512.ll

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