[PATCH] D55448: [DAGCombiner] allow hoisting vector bitwise logic ahead of truncates

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added inline comments.


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Comment at: test/CodeGen/ARM/setcc-logic.ll:28
+; CHECK-NEXT:    lsr r0, r0, #5
+; CHECK-NEXT:    bx lr
   %cmp1 = icmp eq i32 %a, %b
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Is this a NFC regeneration change?


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D55448/new/

https://reviews.llvm.org/D55448