[PATCH] D55558: [TargetLowering] Add ISD::AND handling to SimplifyDemandedVectorElts

[Andrea Di Biagio via Phabricator via llvm-commits]

andreadb accepted this revision.
andreadb added a comment.
This revision is now accepted and ready to land.

Looks good to me.



================
Comment at: test/CodeGen/X86/known-bits-vector.ll:8-11
+; X32-NEXT:    movl $15, %eax
+; X32-NEXT:    vmovd %eax, %xmm1
+; X32-NEXT:    vpand %xmm1, %xmm0, %xmm0
 ; X32-NEXT:    vpextrw $0, %xmm0, %eax
----------------
Unrelated to this patch:

If we know that only element 0 is goign to be used, then - in this case - it is better to move the computation in the Integer unit.

Something like:
```
vpextrw $0, %xmm0, %eax
and $15, %eax
```

In this case, we could avoid to move data back and forth from the integer unit to the floating point unit.



================
Comment at: test/CodeGen/X86/known-signbits-vector.ll:280-283
+; X64-NEXT:    vmovq %rax, %xmm1
 ; X64-NEXT:    vpand %xmm1, %xmm0, %xmm0
 ; X64-NEXT:    vmovq %xmm0, %rax
+; X64-NEXT:    vcvtsi2ssl %eax, %xmm2, %xmm0
----------------
Similar problem.

However, this time we can keep the computation in the FP unit, and avoid data to be bounced back and forth from the two units.

```
vmovq %rax, %xmm1
vpand %xmm1, %xmm0, %xmm0
vcvtdq2ps %xmm0, %xmm0
```

That being said, I suspect that this code can be further simplified (as in: scalarized) if we keep improving the knowledge about demanded vector elements.


Repository:
  rL LLVM

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  https://reviews.llvm.org/D55558/new/

https://reviews.llvm.org/D55558