[PATCH] D55558: [TargetLowering] Add ISD::AND handling to SimplifyDemandedVectorElts

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon created this revision.
RKSimon added reviewers: craig.topper, spatel, jonpa, andreadb.

If either of the operand elements are zero then we know the result element is going to be zero (even if the other element is undef).


Repository:
  rL LLVM

https://reviews.llvm.org/D55558

Files:
  lib/CodeGen/SelectionDAG/TargetLowering.cpp
  test/CodeGen/SystemZ/vec-trunc-to-i1.ll
  test/CodeGen/X86/copysign-constant-magnitude.ll
  test/CodeGen/X86/known-bits-vector.ll
  test/CodeGen/X86/known-signbits-vector.ll
  test/CodeGen/X86/vector-shift-lshr-sub128.ll
  test/CodeGen/X86/vector-shift-shl-sub128.ll

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