[PATCH] D54725: [SelectionDAG] Compute known bits and num sign bits for live out vector registers. Use it to add AssertZExt/AssertSExt in the live in basic blocks

[Sanjay Patel via Phabricator via llvm-commits]

spatel accepted this revision.
spatel added a comment.
This revision is now accepted and ready to land.

In https://reviews.llvm.org/D54725#1303758, @craig.topper wrote:

> This doesn't help PR11730 at all.


Ok, thanks for checking. LGTM.


https://reviews.llvm.org/D54725