[PATCH] D54725: [SelectionDAG] Compute known bits and num sign bits for live out vector registers. Use it to add AssertZExt/AssertSExt in the live in basic blocks

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This revision was automatically updated to reflect the committed changes.
Closed by commit rL347287: [SelectionDAG] Compute known bits and num sign bits for live out vector… (authored by ctopper, committed by ).

Changed prior to commit:
  https://reviews.llvm.org/D54725?vs=174718&id=174721#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D54725

Files:
  llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
  llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
  llvm/trunk/test/CodeGen/X86/vector-mul.ll

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