[PATCH] D53579: [AArch64] Do 64-bit vector move of 0 and -1 by extracting from the 128-bit move

[Dave Green via Phabricator via llvm-commits]

dmgreen accepted this revision.
dmgreen added a comment.
This revision is now accepted and ready to land.

LGTM.

I was thinking about how this might affect other little cores like the A53/A55, especially around the dual issue on q registers. I don't think it will make much difference though, and the CSE benefits look like a bigger win.


Repository:
  rL LLVM

https://reviews.llvm.org/D53579