[PATCH] D53579: [AArch64] Do 64-bit vector move of 0 and -1 by extracting from the 128-bit move

[John Brawn via Phabricator via llvm-commits]

john.brawn created this revision.
john.brawn added reviewers: t.p.northover, olista01, dmgreen, SjoerdMeijer.
Herald added subscribers: kristof.beyls, javed.absar.

Currently a vector move of 0 or -1 will use different instructions depending on the size of the vector. Using a single instruction (the 128-bit one) for both gives more opportunity for Machine CSE to eliminate instructions.


Repository:
  rL LLVM

https://reviews.llvm.org/D53579

Files:
  lib/Target/AArch64/AArch64InstrInfo.td
  test/CodeGen/AArch64/aarch64-be-bv.ll
  test/CodeGen/AArch64/aarch64-smax-constantfold.ll
  test/CodeGen/AArch64/arm64-neon-compare-instructions.ll
  test/CodeGen/AArch64/arm64-neon-copy.ll
  test/CodeGen/AArch64/arm64-vector-ext.ll
  test/CodeGen/AArch64/arm64-vshuffle.ll
  test/CodeGen/AArch64/arm64-zero-cycle-zeroing.ll
  test/CodeGen/AArch64/bitcast.ll
  test/CodeGen/AArch64/fast-isel-cmp-vec.ll
  test/CodeGen/AArch64/fold-constants.ll
  test/CodeGen/AArch64/machine_cse.ll
  test/CodeGen/AArch64/neon-compare-instructions.ll
  test/CodeGen/AArch64/selectiondag-order.ll

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