[PATCH] D53224: [RISCV] Eliminate unnecessary masking of promoted shift amounts

[Eli Friedman via Phabricator via llvm-commits]

efriedma accepted this revision.
efriedma added a comment.
This revision is now accepted and ready to land.

LGTM with a couple more tests with an explicit AND (to show the pattern triggers for "and i32 %shamt, 31", but not "and i32 %shamt, 15").

I think you also need patterns for sraw etc., but I guess you'll do that separately?


https://reviews.llvm.org/D53224