[PATCH] D53224: [RISCV] Eliminate unnecessary masking of promoted shift amounts

[Alex Bradbury via Phabricator via llvm-commits]

asb created this revision.
asb added reviewers: efriedma, sabuasal, apazos.
Herald added subscribers: jocewei, PkmX, rkruppe, the_o, brucehoult, MartinMosbeck, rogfer01, mgrang, edward-jones, zzheng, shiva0217, kito-cheng, niosHD, simoncook, johnrusso, rbar.

SelectionDAGBuilder::visitShift will always zero-extend a shift amount when it is promoted to the ShiftAmountTy. This results in zero-extension (masking) which is unnecessary for RISC-V as the shift operations only read the lower 5 or 6 bits (RV32 or RV64).

I initially proposed adding a getExtendForShiftAmount hook so the shift amount can be any-extended (https://reviews.llvm.org/D52975). @efriedma explained this was unsafe, so I have instead eliminate the unnecessary `and` operations at instruction selection time in a manner similar to X86InstrCompiler.td.


https://reviews.llvm.org/D53224

Files:
  lib/Target/RISCV/RISCVInstrInfo.td
  test/CodeGen/RISCV/alu16.ll
  test/CodeGen/RISCV/alu8.ll

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