[PATCH] D52816: [AArch64] Create proper memoperand for multi-vector stores

[David Greene via Phabricator via llvm-commits]

greened added a comment.

In https://reviews.llvm.org/D52816#1254107, @efriedma wrote:

> You could just directly test that the computed memory operand is correct: write a test that runs "llc -stop-after=isel" and check the MIR.  Without your patch, you should see something like "ST1Fourv2d killed %5, %4 :: (store 48 into %ir.addr, align 64)"; with your patch, that will be "store 64".


Ah yeah, that's a great idea.  I'll do that.  Thanks!


Repository:
  rL LLVM

https://reviews.llvm.org/D52816