[PATCH] D52816: [AArch64] Create proper memoperand for multi-vector stores

[Eli Friedman via Phabricator via llvm-commits]

efriedma added a comment.

You could just directly test that the computed memory operand is correct: write a test that runs "llc -stop-after=isel" and check the MIR.  Without your patch, you should see something like "ST1Fourv2d killed %5, %4 :: (store 48 into %ir.addr, align 64)"; with your patch, that will be "store 64".

I don't think it's necessary to write a test where the final assembly is actually affected by the incorrect memory operand.


Repository:
  rL LLVM

https://reviews.llvm.org/D52816