[PATCH] D50982: [AMDGPU] Legalize VGPR Rsrc operands for MUBUF instructions

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


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Comment at: test/CodeGen/AMDGPU/mubuf-legalize-operands.ll:2
+; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs -o - %s | FileCheck %s
+
+; Test that we correctly legalize VGPR Rsrc operands in MUBUF instructions.
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Probably should have an -O0 run line to make sure spills work correctly. Full check lines for every test for this is probably too exhausting for doing it manually, so maybe just a case with a cross block use


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Comment at: test/CodeGen/AMDGPU/mubuf-legalize-operands.ll:12
+; CHECK-DAG: v_readfirstlane_b32 s[[SRSRC3:[0-9]+]], v3
+; CHECK-NOT: DAG-DIVIDER
+; CHECK-DAG: v_cmp_eq_u64_e32 vcc, s{{\[}}[[SRSRC0]]:[[SRSRC1]]{{\]}}, v[0:1]
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What's this?


https://reviews.llvm.org/D50982