[PATCH] D50982: [AMDGPU] Legalize VGPR Rsrc operands for MUBUF instructions

[Scott Linder via Phabricator via llvm-commits]

scott.linder added a comment.

I think even in the simplest case my code is wrong. The $soffset operand to the BUFFER_LOAD remains killed but the def is not moved into the LoopBB. I am essentially transforming:

  %soffset:sreg_32_xm0 = S_MOV_B32 0
  BUFFER_LOAD ..., killed %soffset:sreg_32_xm0, ...

Into:

  %soffset:sreg_32_xm0 = S_MOV_B32 0
  bb1:
  BUFFER_LOAD ..., killed %soffset:sreg_32_xm0, ...
  S_CBRANCH bb1

Is it correct to just clear the killed flag on the operand? Should I do the same for the $vindex/$voffset/$vaddr operands?



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Comment at: test/CodeGen/AMDGPU/mubuf-legalize-operands.ll:12
+; CHECK-DAG: v_readfirstlane_b32 s[[SRSRC3:[0-9]+]], v3
+; CHECK-NOT: DAG-DIVIDER
+; CHECK-DAG: v_cmp_eq_u64_e32 vcc, s{{\[}}[[SRSRC0]]:[[SRSRC1]]{{\]}}, v[0:1]
----------------
arsenm wrote:
> What's this?
This is me trying to be sure the uses occurs after the defs, even though the order within each doesn't matter. My understanding is that without the divider the cmp's could appear before the readfirstlanes and because they are adjacent -DAG it would still match. The chances of it seem low, and maybe there is a better way than a dummy CHECK-NOT to prevent it?


https://reviews.llvm.org/D50982