[PATCH] D50401: [GISel]: Add Opcodes for a few Libm Intrinsics

[Aditya Nandakumar via Phabricator via llvm-commits]

aditya_nandakumar created this revision.
aditya_nandakumar added reviewers: qcolombet, ab, bogner, aemerson, dsanders, volkan, rtereshin.
Herald added a reviewer: javed.absar.

Add opcodes for llvm.intrinsic.trunc and round (only a couple for now). Opting for a verbose name with LIBM prefix for clarity.


Repository:
  rL LLVM

https://reviews.llvm.org/D50401

Files:
  include/llvm/Support/TargetOpcodes.def
  include/llvm/Target/GenericOpcodes.td
  lib/CodeGen/GlobalISel/IRTranslator.cpp
  test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll


Index: test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
===================================================================
--- test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
+++ test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
@@ -1408,6 +1408,26 @@
   ret float %res
 }
 
+declare float @llvm.trunc.f32(float)
+define float @test_libm_trunc(float %a) {
+; CHECK-LABEL: name: test_libm_trunc
+; CHECK: [[A:%[0-9]+]]:_(s32) = COPY $s0
+; CHECK: [[RES:%[0-9]+]]:_(s32) = G_LIBM_TRUNC [[A]]
+; CHECK: $s0 = COPY [[RES]]
+  %res = call float @llvm.trunc.f32(float %a)
+  ret float %res
+}
+
+declare float @llvm.round.f32(float)
+define float @test_libm_round(float %a) {
+; CHECK-LABEL: name: test_libm_round
+; CHECK: [[A:%[0-9]+]]:_(s32) = COPY $s0
+; CHECK: [[RES:%[0-9]+]]:_(s32) = G_LIBM_ROUND [[A]]
+; CHECK: $s0 = COPY [[RES]]
+  %res = call float @llvm.round.f32(float %a)
+  ret float %res
+}
+
 declare i32 @llvm.ctlz.i32(i32, i1)
 define i32 @test_ctlz_intrinsic_zero_not_undef(i32 %a) {
 ; CHECK-LABEL: name: test_ctlz_intrinsic_zero_not_undef
Index: lib/CodeGen/GlobalISel/IRTranslator.cpp
===================================================================
--- lib/CodeGen/GlobalISel/IRTranslator.cpp
+++ lib/CodeGen/GlobalISel/IRTranslator.cpp
@@ -851,6 +851,16 @@
         .addDef(getOrCreateVReg(CI))
         .addUse(getOrCreateVReg(*CI.getArgOperand(0)));
     return true;
+  case Intrinsic::trunc:
+    MIRBuilder.buildInstr(TargetOpcode::G_LIBM_TRUNC)
+        .addDef(getOrCreateVReg(CI))
+        .addUse(getOrCreateVReg(*CI.getArgOperand(0)));
+    return true;
+  case Intrinsic::round:
+    MIRBuilder.buildInstr(TargetOpcode::G_LIBM_ROUND)
+        .addDef(getOrCreateVReg(CI))
+        .addUse(getOrCreateVReg(*CI.getArgOperand(0)));
+    return true;
   case Intrinsic::fma:
     MIRBuilder.buildInstr(TargetOpcode::G_FMA)
         .addDef(getOrCreateVReg(CI))
Index: include/llvm/Target/GenericOpcodes.td
===================================================================
--- include/llvm/Target/GenericOpcodes.td
+++ include/llvm/Target/GenericOpcodes.td
@@ -512,6 +512,21 @@
   let hasSideEffects = 0;
 }
 
+//------------------------------------------------------------------------------
+// LIBM Intrinsics
+//------------------------------------------------------------------------------
+def G_LIBM_TRUNC : GenericInstruction {
+  let OutOperandList = (outs type0:$dst);
+  let InOperandList = (ins type0:$src1);
+  let hasSideEffects = 0;
+}
+
+def G_LIBM_ROUND : GenericInstruction {
+  let OutOperandList = (outs type0:$dst);
+  let InOperandList = (ins type0:$src1);
+  let hasSideEffects = 0;
+}
+
 //------------------------------------------------------------------------------
 // Memory ops
 //------------------------------------------------------------------------------
Index: include/llvm/Support/TargetOpcodes.def
===================================================================
--- include/llvm/Support/TargetOpcodes.def
+++ include/llvm/Support/TargetOpcodes.def
@@ -268,6 +268,12 @@
 /// COPY is the relevant instruction.
 HANDLE_TARGET_OPCODE(G_BITCAST)
 
+/// LIBM trunc intrinsic.
+HANDLE_TARGET_OPCODE(G_LIBM_TRUNC)
+
+/// LIBM round intrinsic.
+HANDLE_TARGET_OPCODE(G_LIBM_ROUND)
+
 /// Generic load (including anyext load)
 HANDLE_TARGET_OPCODE(G_LOAD)
 


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