[PATCH] D49994: Allow constraining virtual register's class within reason

[Alexey Zhikhartsev via Phabricator via llvm-commits]

alexey.zhikhar added a comment.

In https://reviews.llvm.org/D49994#1191386, @efriedma wrote:

> I'd like an explanation for why the generated code is changing for AArch64... generating extra copies clearly seems like a downside.  And there isn't any obvious reason for this change to impact register allocation: on AArch64, all i32 register classes contain exactly the same set of allocatable registers.


Agreed. ARM people might have some thoughts of what the root cause might be, and I'd love to investigate the leads.


https://reviews.llvm.org/D49994