[PATCH] D49778: Fix "Q" and "R" inline assembly template modifiers for big-endian Arm

[Jackson Woodruff via Phabricator via llvm-commits]

Jackson updated this revision to Diff 157970.
Jackson added a comment.

Thanks for the review Thomas.  I have update the diff so it has context, and have fixed the formatting issue.   I think the if statement is probably better as is, although I'm also not entirely sure.


Repository:
  rL LLVM

https://reviews.llvm.org/D49778

Files:
  lib/Target/ARM/ARMAsmPrinter.cpp
  test/CodeGen/ARM/print-registers-be.ll


Index: test/CodeGen/ARM/print-registers-be.ll
===================================================================
--- /dev/null
+++ test/CodeGen/ARM/print-registers-be.ll
@@ -0,0 +1,12 @@
+; RUN: llc -mtriple=armeb-arm-none-eabi < %s -o -| FileCheck %s
+
+define dso_local void @_Z3fooi(i32 %a) local_unnamed_addr #0 {
+entry:
+; CHECK:	@ plain: [[LOW_REG:r[0-9]+]]
+; CHECK:	@ Q: [[HIGH_REG:r[0-9]+]]
+; CHECK:	@ R: [[LOW_REG]]
+; CHECK:	@ H: [[HIGH_REG]]
+  tail call void asm sideeffect "\0A      // plain: $0\0A      // Q: ${0:Q}\0A      // R: ${0:R}\0A      // H: ${0:H}\0A    ", "r"(i64 1) #1
+  ret void
+}
+
Index: lib/Target/ARM/ARMAsmPrinter.cpp
===================================================================
--- lib/Target/ARM/ARMAsmPrinter.cpp
+++ lib/Target/ARM/ARMAsmPrinter.cpp
@@ -358,22 +358,32 @@
 
       unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
       unsigned RC;
+      bool FirstHalf;
+      const ARMBaseTargetMachine &ATM =
+        static_cast<const ARMBaseTargetMachine &>(TM);
       InlineAsm::hasRegClassConstraint(Flags, RC);
+      if (ExtraCode[0] == 'Q') {
+        FirstHalf = ATM.isLittleEndian();
+      } else {
+        // ExtraCode[0] == 'R'.
+        FirstHalf = !ATM.isLittleEndian();
+      }
+
       if (RC == ARM::GPRPairRegClassID) {
         if (NumVals != 1)
           return true;
         const MachineOperand &MO = MI->getOperand(OpNum);
         if (!MO.isReg())
           return true;
         const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
-        unsigned Reg = TRI->getSubReg(MO.getReg(), ExtraCode[0] == 'Q' ?
+        unsigned Reg = TRI->getSubReg(MO.getReg(), FirstHalf ?
             ARM::gsub_0 : ARM::gsub_1);
         O << ARMInstPrinter::getRegisterName(Reg);
         return false;
       }
       if (NumVals != 2)
         return true;
-      unsigned RegOp = ExtraCode[0] == 'Q' ? OpNum : OpNum + 1;
+      unsigned RegOp = FirstHalf ? OpNum : OpNum + 1;
       if (RegOp >= MI->getNumOperands())
         return true;
       const MachineOperand &MO = MI->getOperand(RegOp);


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