[PATCH] D49280: [X86] Remove isel patterns for MOVSS/MOVSD ISD opcodes with integer types.

[Roman Lebedev via Phabricator via llvm-commits]

lebedev.ri added a comment.

In https://reviews.llvm.org/D49280#1163648, @RKSimon wrote:

> In https://reviews.llvm.org/D49280#1162909, @craig.topper wrote:
>
> > Which microarchitecture cares about switching PD/PS? To my knowledge, no Intel architecture cares. Do any of the AMD architectures care?
>
>
> It tends to be only the 'weird mixture' PS/PD domain shifts that cause a stall: VADDPS then VMULPD, that kind of thing - shuffles and bitops tend to be more forgiving (and more easy to fix.)


http://www.agner.org/optimize/microarchitecture.pdf, "21 AMD Bobcat and Jaguar pipeline", page 222:

  21.9 Data delay between differently typed instructions
  ...
  There is a penalty of 40 clock cycles when the output of a floating point calculation is input
  to a floating point calculation with a different precision, for example if the output of a double
  precision floating point addition is input to a single precision addition. This has hardly any
  practical significance since such a sequence is most likely to be a programming error, but it
  indicates that the processor stores extra information about floating point numbers beyond
  the 128 bits in an XMM register.


Repository:
  rL LLVM

https://reviews.llvm.org/D49280