[PATCH] D49280: [X86] Remove isel patterns for MOVSS/MOVSD ISD opcodes with integer types.

[David Greene via Phabricator via llvm-commits]

greened added a comment.

In https://reviews.llvm.org/D49280#1163648, @RKSimon wrote:

> In https://reviews.llvm.org/D49280#1162909, @craig.topper wrote:
>
> > Which microarchitecture cares about switching PD/PS? To my knowledge, no Intel architecture cares. Do any of the AMD architectures care?
>
>
> It tends to be only the 'weird mixture' PS/PD domain shifts that cause a stall: VADDPS then VMULPD, that kind of thing - shuffles and bitops tend to be more forgiving (and more easy to fix.)


The AMD 17h Optimization Guide has this to say:

"Try to use consistent data types for instructions operating on the same data. For example, use 
VANDPS, VMAXPS, and so on when consuming the output of MULPS."

The inclusion of VANDPS in that list makes me think all such domain crossings may incur a penalty.
I have not seen an explicit list anywhere of what is and is not bad.  A VADDPD feeding a VANDPS
is probably not a programming error but it would incur a penalty.


Repository:
  rL LLVM

https://reviews.llvm.org/D49280