[PATCH] D48580: [AArch64] Support reserving x1-7 registers.

[Eli Friedman via Phabricator via llvm-commits]

efriedma added a comment.

> Shouldn't this be implemented as a function attribute to make sure this won't break in LTO builds?

You can express target features as function attributes: `"target-features"="+reserve-x1" etc.  Maybe worth adding a testcase to show that works.

> the compiler giving an error may prevent the user from doing something he understands and needs to be done and cannot be achieved in any other way

I'm mostly worried we'll end up in situations where the option appears to work, but then miscompiles with a newer compiler, or different optimization options.  For example, the code you explicitly wrote doesn't pass arguments in x7, but argpromotion increases the number of arguments to a function.  Or your code doesn't pass arguments in x2, but -Os makes a struct assignment lower to a call to memcpy instead of expanding the copy inline.  Or a user tries to reserve x16, we outline some code, and the linker inserts a stub that clobbers x16.


Repository:
  rL LLVM

https://reviews.llvm.org/D48580