[PATCH] D44548: [DAGCombiner] Expand combining of FP logical operations to sign-setting FP operations

[Eli Friedman via Phabricator via llvm-commits]

efriedma added a comment.

AArch64 doesn't have a nabs instruction; orr is probably faster than fabs+fneg (unless some implementations have a transition penalty between int SIMD and float SIMD).  But we could accept fneg(fabs(x)) as the canonical form and pattern-match it.


Repository:
  rL LLVM

https://reviews.llvm.org/D44548