[PATCH] D44548: [DAGCombiner] Expand combining of FP logical operations to sign-setting FP operations

[Nemanja Ivanovic via Phabricator via llvm-commits]

nemanjai added a comment.

In https://reviews.llvm.org/D44548#1116753, @efriedma wrote:

> AArch64 doesn't have a nabs instruction; orr is probably faster than fabs+fneg (unless some implementations have a transition penalty between int SIMD and float SIMD).  But we could accept fneg(fabs(x)) as the canonical form and pattern-match it.


If you think it's worthwhile, I could make `hasBitPreservingFPLogic()` return an `enum` with `None, FabsOnly, FnegOnly, SingleNodeOnly, All` or something along those lines... and then use that to guide which transformations to actually apply.



================
Comment at: lib/CodeGen/SelectionDAG/DAGCombiner.cpp:8933
+  // For vector nodes, the input must be a constant splat build vector and the
+  // splat value must be equal to SignMask.
+  if (IsVector) {
----------------
RKSimon wrote:
> We have ISD::isConstOrConstSplat - can we use that instead and merge these 2 paths?
I think that will fail if some of the elements are `undef`. And that seems unnecessary. Something like this:
```
  %conv = bitcast <4 x float> %a to <4 x i32>
  %and = and <4 x i32> %conv, <i32 2147483647, i32 undef, i32 undef, i32 2147483647>
```
should be perfectly fine to transform.


Repository:
  rL LLVM

https://reviews.llvm.org/D44548