[PATCH] D46528: [DAGCombine][X86][AArch64] Masked merge unfolding: vector edition.

[Roman Lebedev via Phabricator via llvm-commits]

lebedev.ri added inline comments.


================
Comment at: lib/Target/X86/X86ISelLowering.cpp:4773-4776
+  if (VT == MVT::v4i32)
+    return true;
+
+  return Subtarget.hasSSE2();
----------------
spatel wrote:
> That seems odd. Does something bad happen with other types of 128-bit vectors (eg v8i16) with SSE1 only? I would've thought all element types would get mapped to andnps.
I'm pretty sure that with SSE1 we only get this vector size.
https://godbolt.org/g/o5CGQt

https://software.intel.com/sites/landingpage/IntrinsicsGuide/#techs=SSE,SSE2&text=andn
http://www.felixcloutier.com/x86/ANDNPS.html
http://www.felixcloutier.com/x86/ANDNPD.html


Repository:
  rL LLVM

https://reviews.llvm.org/D46528