[PATCH] D46528: [DAGCombine][X86][AArch64] Masked merge unfolding: vector edition.

[Sanjay Patel via Phabricator via llvm-commits]

spatel added a reviewer: RKSimon.
spatel added inline comments.


================
Comment at: lib/Target/AArch64/AArch64ISelLowering.h:444
 
-  bool hasAndNotCompare(SDValue) const override {
-    // 'bics'
-    return true;
+  bool hasAndNotCompare(SDValue Y) const override {
+    EVT VT = Y.getValueType();
----------------
The name of the function is overly specific if we're including bsl and instructions too. I think we should either generalize that name or add a different hook for "hasBitwiseSelect".


================
Comment at: lib/Target/X86/X86ISelLowering.cpp:4773-4776
+  if (VT == MVT::v4i32)
+    return true;
+
+  return Subtarget.hasSSE2();
----------------
That seems odd. Does something bad happen with other types of 128-bit vectors (eg v8i16) with SSE1 only? I would've thought all element types would get mapped to andnps.


Repository:
  rL LLVM

https://reviews.llvm.org/D46528