[PATCH] D42033: [RISCV] Initial Machine Scheduler

[Leslie Zhai via Phabricator via llvm-commits]

xiangzhai added inline comments.


================
Comment at: lib/Target/RISCV/RISCVSchedule.td:18
+
+// Basic ALU with shifts.
+def WriteALUsi : SchedWrite; // Shift by immediate.
----------------
javed.absar wrote:
> These definitions may be ok for a start, but you would need to decide what best fits your purpose (maybe fewer SchedWriteTypes to begin with ?)
My sincere thanks still need to goto you for reviewing D39712 even it is not LGTM :)


Repository:
  rL LLVM

https://reviews.llvm.org/D42033