[PATCH] D42033: [RISCV] Initial Machine Scheduler

[Leslie Zhai via Phabricator via llvm-commits]

xiangzhai added inline comments.


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Comment at: lib/Target/RISCV/RISCVScheduleGRV32.td:25
+// Functional units
+def GRV32_Issue0  : FuncUnit; // Issue 0
+def GRV32_Issue1  : FuncUnit; // Issue 1
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javed.absar wrote:
> Why not ProcResource?
Hi Javed,

Thanks for your review and great tutorial about [Writing Great Machine Schedulers](http://llvm.org/devmtg/2017-10/#tutorial1) !

As my comment `FIXME` mentioned:

> I have no idea how to find scheduling information, perhaps some RV32 Technical Reference Manual provided?

So I am reading gcc riscv Target's [Generic DFA-based pipeline](https://github.com/gcc-mirror/gcc/blob/master/gcc/config/riscv/generic.md) without manual, it is like AVR Target migate to LLD, there is no ABI manual either, so I have to borrow code from binutils in D37615 .

I want to learn and practice, please leading me, thanks a lot!

Regards,
Leslie Zhai


Repository:
  rL LLVM

https://reviews.llvm.org/D42033