[PATCH] D42033: [RISCV] Initial Machine Scheduler

[Alex Bradbury via Phabricator via llvm-commits]

asb added a comment.

Leslie - there's a huge amount here that's copied and pasted from ARMScheduleA9.td, much of it really isn't relevant to any current RISC-V implementation, such as load-multiple/store-multiple and vector operations. Additionally, the A9 is an out-of-order superscalar core. The majority of the RISC-V community are targeting in-order cores (Rocket, PULP, other microcontroller class cores). If you're keen to explore scheduling models for out-of-order cores then BOOM is of course the obvious target.

This patch is intermingled with other changes that you have for review (e.g. calling convention implementation changes, globalisel) - it's always best to post a diff that only contains the changes needed for this particular review.

What you've done here is a good start for getting a better understanding of how machine scheduling works. What I think you need to do now is figure out what sort of scheduling model you want to write (e.g. for the default configuration of Rocket), and how you can write tests that demonstrate the model is doing what it is meant to do, then you can try to produce something that's a little more minimal than what you have here. I don't have enough experience with LLVM scheduling models to predict how much there might be to gain for a pipeline as simple as Rocket. It's single-issue in-order, but does have a non-blocking https://reviews.llvm.org/L1 cache which allows the pipeline to continue under a cache miss until there is a dependency on the result.


Repository:
  rL LLVM

https://reviews.llvm.org/D42033