[PATCH] D42033: [RISCV] Initial Machine Scheduler

[Javed Absar via Phabricator via llvm-commits]

javed.absar added inline comments.


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Comment at: lib/Target/RISCV/RISCVSchedule.td:18
+
+// Basic ALU with shifts.
+def WriteALUsi : SchedWrite; // Shift by immediate.
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These definitions may be ok for a start, but you would need to decide what best fits your purpose (maybe fewer SchedWriteTypes to begin with ?)


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Comment at: lib/Target/RISCV/RISCVScheduleGRV32.td:25
+// Functional units
+def GRV32_Issue0  : FuncUnit; // Issue 0
+def GRV32_Issue1  : FuncUnit; // Issue 1
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Why not ProcResource?


Repository:
  rL LLVM

https://reviews.llvm.org/D42033