[PATCH] D40511: [AArch64] Fix scheduling resources for post indexed loads and stores

[Evandro Menezes via Phabricator via llvm-commits]

evandro added a comment.

In https://reviews.llvm.org/D40511#974794, @qcolombet wrote:

> I don't expect you have a test case that exposed the problem, right?
>  (In particular for Cyclone at least WriteAdr is the same as WriteI).


I noticed this issue when working in https://reviews.llvm.org/D39976, where otherwise test cases fail without this change.

Thank you.


Repository:
  rL LLVM

https://reviews.llvm.org/D40511