[PATCH] D40511: [AArch64] Fix scheduling resources for post indexed loads and stores

[Quentin Colombet via Phabricator via llvm-commits]

qcolombet accepted this revision.
qcolombet added a comment.
This revision is now accepted and ready to land.

LGTM.

I don't expect you have a test case that exposed the problem, right?
(In particular for Cyclone at least WriteAdr is the same as WriteI).


Repository:
  rL LLVM

https://reviews.llvm.org/D40511