[PATCH] D40511: [AArch64] Fix scheduling resources for post indexed loads and stores
Evandro Menezes via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Fri Jan 12 11:21:32 PST 2018
This revision was automatically updated to reflect the committed changes.
Closed by commit rL322392: [AArch64] Fix scheduling resources for post indexed loads and stores (authored by evandro, committed by ).
Changed prior to commit:
https://reviews.llvm.org/D40511?vs=124433&id=129673#toc
Repository:
rL LLVM
https://reviews.llvm.org/D40511
Files:
llvm/trunk/lib/Target/AArch64/AArch64InstrFormats.td
Index: llvm/trunk/lib/Target/AArch64/AArch64InstrFormats.td
===================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64InstrFormats.td
+++ llvm/trunk/lib/Target/AArch64/AArch64InstrFormats.td
@@ -3376,7 +3376,7 @@
(outs GPR64sp:$wback, regtype:$Rt),
(ins GPR64sp:$Rn, simm9:$offset),
asm, "$Rn = $wback, at earlyclobber $wback", []>,
- Sched<[WriteLD, WriteI]>;
+ Sched<[WriteLD, WriteAdr]>;
let mayStore = 1, mayLoad = 0 in
class StorePostIdx<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
@@ -3387,7 +3387,7 @@
asm, "$Rn = $wback, at earlyclobber $wback",
[(set GPR64sp:$wback,
(storeop (Ty regtype:$Rt), GPR64sp:$Rn, simm9:$offset))]>,
- Sched<[WriteAdr, WriteST, ReadAdrBase]>;
+ Sched<[WriteAdr, WriteST]>;
} // hasSideEffects = 0
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