[PATCH] D40805: [RISCV] Support for varargs

[Leslie Zhai via Phabricator via llvm-commits]

xiangzhai added inline comments.


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Comment at: lib/Target/RISCV/RISCVISelLowering.cpp:701
+    // If saving an odd-number of registers, create an extra stack slot to
+    // ensure even-numbered registers are always 2*XLEN-aligned.
+    if (Idx % 2) {
----------------
efriedma wrote:
> Could you clarify what "ensure even-numbered registers are always 2*XLEN-aligned" means?  The varargs save area is always right next to any arguments passed on the stack, so I'm not sure what exactly you need to align.
Hi Eli,

I am reviewing [Compiler Principle](https://en.wikipedia.org/wiki/Compilers:_Principles,_Techniques,_and_Tools) chapter 7.2 Stack Allocation, then consider about this question, because Strict Alignment? just like GCC https://gcc.gnu.org/ml/gcc-patches/2017-05/msg00011.html Please teach me, thanks a lot!

Regards,
Leslie Zhai 


https://reviews.llvm.org/D40805