[PATCH] D40805: [RISCV] Support for varargs

[Eli Friedman via Phabricator via llvm-commits]

efriedma added inline comments.


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Comment at: lib/Target/RISCV/RISCVISelLowering.cpp:701
+    // If saving an odd-number of registers, create an extra stack slot to
+    // ensure even-numbered registers are always 2*XLEN-aligned.
+    if (Idx % 2) {
----------------
xiangzhai wrote:
> efriedma wrote:
> > Could you clarify what "ensure even-numbered registers are always 2*XLEN-aligned" means?  The varargs save area is always right next to any arguments passed on the stack, so I'm not sure what exactly you need to align.
> Hi Eli,
> 
> I am reviewing [Compiler Principle](https://en.wikipedia.org/wiki/Compilers:_Principles,_Techniques,_and_Tools) chapter 7.2 Stack Allocation, then consider about this question, because Strict Alignment? just like GCC https://gcc.gnu.org/ml/gcc-patches/2017-05/msg00011.html Please teach me, thanks a lot!
> 
> Regards,
> Leslie Zhai 
Yes, in general, some things need to be aligned, for a variety of reasons (including the issue you noted).  I'm not questioning that part.

The question is more about the stack layout.  Why do we need to allocate an extra object here to ensure alignment?  What stack objects are we ensuring the alignment of?


https://reviews.llvm.org/D40805