[PATCH] D40805: [RISCV] Support for varargs

[Eli Friedman via Phabricator via llvm-commits]

efriedma added inline comments.


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Comment at: lib/Target/RISCV/RISCVISelLowering.cpp:701
+    // If saving an odd-number of registers, create an extra stack slot to
+    // ensure even-numbered registers are always 2*XLEN-aligned.
+    if (Idx % 2) {
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Could you clarify what "ensure even-numbered registers are always 2*XLEN-aligned" means?  The varargs save area is always right next to any arguments passed on the stack, so I'm not sure what exactly you need to align.


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Comment at: test/CodeGen/RISCV/vararg.ll:3
+; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
+; RUN:   | FileCheck -check-prefix=RV32I %s
+
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Could you generate 64-bit tests as well?  (It probably isn't that different, but nice to have.)


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Comment at: test/CodeGen/RISCV/vararg.ll:297
+; RV32I-NEXT:    sw s0, 16(sp)
+; RV32I-NEXT:    addi s0, sp, 24
+; RV32I-NEXT:    sw a7, 20(s0)
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This looks a little weird; why are we loading sp+24 into a scratch register?


https://reviews.llvm.org/D40805