[PATCH] D41721: [X86] Move HasNOPL to a subtarget feature bit. Plumb MCSubtargetInfo through the MCAsmBackend constructor

[Craig Topper via Phabricator via llvm-commits]

craig.topper updated this revision to Diff 128636.
craig.topper added a comment.

Limit NOP length to 10 on everything but AMD fam 16h and 17h. @RKSimon you mentioned fam 15h in your previous update, but the optimization manual I found for fam 15h only talks about 11 byte.

We could maybe go to 11 instead of 10. But Intel documentation only lists out to 9 bytes. And the current 10-15 byte sequences we do are different than the 10-15 byte sequences in AMD's manual. We use a CS prefix that's not mentioned in the optimization manuals. The CS prefix does appear in the binutils 10 byte sequence. I believe binutils stops at 10 bytes for all CPUs.


https://reviews.llvm.org/D41721

Files:
  lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp
  lib/Target/X86/X86.td
  lib/Target/X86/X86Subtarget.cpp
  lib/Target/X86/X86Subtarget.h
  test/MC/MachO/x86_32-optimal_nop.s
  test/MC/X86/AlignedBundling/long-nop-pad.s
  test/MC/X86/AlignedBundling/misaligned-bundle-group.s
  test/MC/X86/AlignedBundling/misaligned-bundle.s
  test/MC/X86/AlignedBundling/pad-bundle-groups.s
  test/MC/X86/x86_long_nop.s

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D41721.128636.patch
Type: text/x-patch
Size: 21109 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20180104/551f4d72/attachment.bin>