[PATCH] D41441: [AArch64][SVE] Asm: Add restricted register classes for SVE predicate vectors.

Florian Hahn via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Tue Jan 2 09:09:16 PST 2018

fhahn accepted this revision.
fhahn added a comment.
This revision is now accepted and ready to land.

LGTM. Thanks Javed & Sander


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