[PATCH] D41441: [AArch64][SVE] Asm: Add restricted register classes for SVE predicate vectors.

Sander de Smalen via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Tue Jan 2 06:43:29 PST 2018

sdesmalen added inline comments.

Comment at: lib/Target/AArch64/AArch64RegisterInfo.td:771
+  let Size = 16;
javed.absar wrote:
> Looks like some code duplication between PPR and PPR_3b could be factored out by creating an intermediate class. You may want to consider it.
Thanks for the suggestion @javed.absar , I've updated the patch.


More information about the llvm-commits mailing list