[PATCH] D40145: [RISCV] Fix 64-bit data layout mismatch between backend and target description

[Alex Bradbury via Phabricator via llvm-commits]

asb accepted this revision.
asb added a comment.
This revision is now accepted and ready to land.

This is the correct string, as used and tested in the yet-to-be merged patches. I forgot to move this fix from the relevant RV64I patch <https://github.com/lowRISC/riscv-llvm/blob/81359b9c79600bdd7bb2a2ff3579a637cf4534ea/0046-RISCV-Add-initial-RV64I-codegen-support.patch>. Thanks for noticing this.


Repository:
  rL LLVM

https://reviews.llvm.org/D40145