[PATCH] D40145: [RISCV] Fix 64-bit data layout mismatch between backend and target description

[Mandeep Singh Grang via Phabricator via llvm-commits]

mgrang created this revision.
Herald added subscribers: jordy.potman.lists, simoncook, johnrusso, rbar.

Repository:
  rL LLVM

https://reviews.llvm.org/D40145

Files:
  lib/Target/RISCV/RISCVTargetMachine.cpp


Index: lib/Target/RISCV/RISCVTargetMachine.cpp
===================================================================
--- lib/Target/RISCV/RISCVTargetMachine.cpp
+++ lib/Target/RISCV/RISCVTargetMachine.cpp
@@ -30,7 +30,7 @@
 
 static std::string computeDataLayout(const Triple &TT) {
   if (TT.isArch64Bit()) {
-    return "e-m:e-i64:64-n32:64-S128";
+    return "e-m:e-p:64:64-i64:64-i128:128-n64-S128";
   } else {
     assert(TT.isArch32Bit() && "only RV32 and RV64 are currently supported");
     return "e-m:e-p:32:32-i64:64-n32-S128";


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